CaltechAUTHORS
  A Caltech Library Service

Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches

DeHon, André (2005) Deterministic Addressing of Nanoscale Devices Assembled at Sublithographic Pitches. IEEE Transactions on Nanotechnology, 4 (6). pp. 681-687. ISSN 1536-125X. http://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05b

[img]
Preview
PDF
See Usage Policy.

375Kb

Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05b

Abstract

Multiple techniques have now been proposed using random addressing to build demultiplexers which interface between the large pitch of lithographically patterned features and the smaller pitch of self-assembled sublithographic nanowires. At the same time, the relatively high defect rates expected for molecular-sized devices and wires dictate that we design architectures with spare components so we can map around defective elements. To accommodate and mask both of these effects, we introduce a programmable addressing scheme which can be used to provide deterministic addresses for decoders built with random nanoscale addressing and potentially defective wires. We describe how this programmable addressing scheme can be implemented with emerging, nanoscale building blocks and show how to build deterministically addressable memory banks. We characterize the area required for this programmable addressing scheme. For 2048 x 2048 memory banks, the area overhead for address correction is less than 33%, delivering net memory densities around 10^11 b/cm^2.


Item Type:Article
Additional Information:“©2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.” Manuscript received December 1, 2003; revised June 30, 2005. This work was supported by the DARPA Moletronics Program under Grant ONR N00014-01-0651. Architecture work at this early stage is only feasible and meaningful in close cooperation with scientists working on device properties and fabrication. Special thanks to C. Lieber for his support for this research and design.
Subject Keywords:Defect tolerance, electronic nanotechnology, molecular electronics, stochastic assembly
Record Number:CaltechAUTHORS:DEHieeetn05b
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05b
Alternative URL:http://dx.doi.org/10.1109/TNANO.2005.858587
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:1026
Collection:CaltechAUTHORS
Deposited By: Archive Administrator
Deposited On:04 Apr 2006
Last Modified:26 Dec 2012 08:42

Repository Staff Only: item control page