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Nonphotolithographic nanoscale memory density prospects

DeHon, André and Goldstein, Seth Copen and Kuekes, Philip J. (2005) Nonphotolithographic nanoscale memory density prospects. IEEE Transactions on Nanotechnology, 4 (2). pp. 215-228. ISSN 1536-125X. http://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05a

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Abstract

Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active power requirements under 0.6 W/Tb/s for random read operations.


Item Type:Article
Additional Information:“©2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.” Manuscript received December 1, 2003; revised June 28, 2004. This work was supported by the Defense Advanced Research Projects Agency Moletronics Program under Grant ONR N00014-01-0651, Grant MDA972-01-03-0005, and Grant ONR N00014-01-0659. Architecture work at this early stage is only feasible and meaningful in close cooperation with scientists working on device properties and fabrication. Special thanks to J. Heath, C. Lieber, S. Williams, and D. Stewart for their support in this work. The authors are also grateful to M. Ziegler and J. Ellenbogen for drawing attention to some of the parasitic coupling effects in the diode memory banks. The anonymous reviewers made good observations and suggestions that helped make this a more complete and accessible paper.
Subject Keywords:Defect tolerance, electronic nanotechnology, memory density, memory organization, molecular electronics
Record Number:CaltechAUTHORS:DEHieeetn05a
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:DEHieeetn05a
Alternative URL:http://dx.doi.org/10.1109/TNANO.2004.837849
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:1029
Collection:CaltechAUTHORS
Deposited By: Archive Administrator
Deposited On:02 Dec 2005
Last Modified:26 Dec 2012 08:42

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