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Design of FPGA interconnect for multilevel metallization

DeHon, André and Rubin, Raphael (2004) Design of FPGA interconnect for multilevel metallization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12 (10). pp. 1038-1050. ISSN 1063-8210. http://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04a

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Abstract

How does multilevel metallization impact the design of field-programmable gate arrays (FPGA) interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third dimension to reduce area and switch requirements. Unfortunately, traditional FPGA wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topology, based on Leighton's mesh-of-trees (MoT), which carefully exploits hierarchy to allow additional metal layers to support arbitrary device scaling. When wiring layers grow sufficiently fast with aggregate network size (N), our network requires only O(N) area; this is in stark contrast to traditional, Manhattan FPGA routing schemes where switching requirements alone grow superlinearly in N. In practice, we show that, even for the admittedly small designs in the Toronto "FPGA Place and Route Challenge," arity-4 MoT networks require 26% fewer switches than the standard, Manhattan FPGA routing scheme.


Item Type:Article
Additional Information:“©2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.” Manuscript received September 10, 2003; revised January 3, 2004. This research was funded in part by the Defense Advanced Research Projects Agency (DARPA) Moletronics Program under Grant ONR N00014-01-0651 and in part by the National Science Foundation CAREER program under Grant CCR-0133102.
Subject Keywords:Field programmable gate array (FPGA), hierarchical, interconnect, mesh-of-trees (MoT), multilevel metallization, Rent’s rule
Record Number:CaltechAUTHORS:DEHieeetvlsis04a
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04a
Alternative URL:http://dx.doi.org/10.1109/TVLSI.2004.827562
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:1031
Collection:CaltechAUTHORS
Deposited By: Archive Administrator
Deposited On:02 Dec 2005
Last Modified:26 Dec 2012 08:42

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