CaltechAUTHORS
  A Caltech Library Service

Unifying mesh- and tree-based programmable interconnect

DeHon, André (2004) Unifying mesh- and tree-based programmable interconnect. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12 (10). pp. 1051-1065. ISSN 1063-8210. http://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04b

[img]
Preview
PDF
See Usage Policy.

1404Kb

Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04b

Abstract

We examine the traditional, symmetric, Manhattan mesh design for field-programmable gate-array (FPGA) routing along with tree-of-meshes (ToM) and mesh-of-trees (MoT) based designs. All three networks can provide general routing for limited bisection designs (Rent's rule with p<1) and allow locality exploitation. They differ in their detailed topology and use of hierarchy. We show that all three have the same asymptotic wiring requirements. We bound this tightly by providing constructive mappings between routes in one network and routes in another. For example, we show that a (c,p) MoT design can be mapped to a (2c,p) linear population ToM and introduce a corner turn scheme which will make it possible to perform the reverse mapping from any (c,p) linear population ToM to a (2c,p) MoT augmented with a particular set of corner turn switches. One consequence of this latter mapping is a multilayer layout strategy for N-node, linear population ToM designs that requires only /spl Theta/(N) two-dimensional area for any p when given sufficient wiring layers. We further show upper and lower bounds for global mesh routes based on recursive bisection width and show these are within a constant factor of each other and within a constant factor of MoT and ToM layout area. In the process we identify the parameters and characteristics which make the networks different, making it clear there is a unified design continuum in which these networks are simply particular regions.


Item Type:Article
Additional Information:“©2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.” Manuscript received September 10, 2003; revised February 15, 2004. This work was funded in part by the Defense Advanced Research Project Agency (DARPA) Moletronics Program under Grant ONR N00014-01-0651 and by the National Science Foundation CAREER Program under Grant CCR-0133102.
Subject Keywords:Butterfly fat tree (BFT), fat pyramid, fat tree, field-programmable gate-array (FPGA), hierarchical, hierarchical synchronous reconfigurable array (HSRA), interconnect, Manhattan, mesh, mesh-of-trees (MoT), multilevel metallization, Rent’s rule, tree-of-meshes (ToM)
Record Number:CaltechAUTHORS:DEHieeetvlsis04b
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04b
Alternative URL:http://dx.doi.org/10.1109/TVLSI.2004.834237
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:1032
Collection:CaltechAUTHORS
Deposited By: Archive Administrator
Deposited On:02 Dec 2005
Last Modified:26 Dec 2012 08:42

Repository Staff Only: item control page