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CMOS transceiver with baud rate clock recovery for optical interconnects

Emami-Neyestanak, Azita and Palermo, Samuel and Lee, Hae-Chang and Horowitz, Mark (2004) CMOS transceiver with baud rate clock recovery for optical interconnects. In: Symposium on VLSI Circuits, 2004. Digest of Technical Papers. IEEE , Piscataway, NJ, pp. 410-413. ISBN 0-7803-8287-0 http://resolver.caltech.edu/CaltechAUTHORS:EMAvlsic04

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Abstract

An efficient baud rate clock and data recovery architecture is applied to a double sampling/integrating front-end receiver for optical interconnects. Receiver performance is analyzed and projected for future technologies. This front-end allows use of a 1:5 demux architecture to achieve 5Gb/s in a 0.25 μm CMOS process. A 5:1 multiplexing transmitter is used to drive VCSELs for optical transmission. The transceiver chip consumes 145mW per link at 5Gb/s with a 2.5V supply.


Item Type:Book Section
Additional Information:© 2004 IEEE. Reprinted with Permission. Publication Date: 17-19 June 2004. Posted online: 2004-10-25. The authors would like to thank Jaeha Kim, Elad Alon, Aparna Bhatnagar and Tim Drabik for technical discussions, National Semiconductor for fabrication of the test chip, and NSF, TI, DARPA, and the MARCO Interconnect Focus Center for funding.
Subject Keywords:optical interconnects; clock and data recovery; integrating receiver; I/O; double sampling; baud rate; VCSEL
Record Number:CaltechAUTHORS:EMAvlsic04
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:EMAvlsic04
Alternative URL:http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=29642&arnumber=1346633&count=116&index=104
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:10570
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:19 May 2008
Last Modified:19 May 2014 18:48

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