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A 10Gb/s eye-opening monitor in 0.13μm CMOS

Analui, Behnam and Rylyakov, Alexander and Rylov, Sergey and Meghelli, Mounir and Hajimiri, Ali (2005) A 10Gb/s eye-opening monitor in 0.13μm CMOS. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers. ISSCC '05. San Francisco, CA. Vol.1. IEEE , Piscataway, NJ, 332-333 + 602. ISBN 0780389042

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An eye-opening monitor circuit in 0.13 μm CMOS operates from 1 to 12.5Gbit/s at 1.2V supply. It maps the input eye to a 2D error diagram with 68dB mask error dynamic range. Left and right halt of the eye are monitored separately to capture asymmetric eyes. Tested input amplitude is from 50 to 400mV. The chip consumes 330mW and works at 10Gb/s with a supply voltage as low as 1V.

Item Type:Book Section
Additional Information:© Copyright 2005 IEEE. Reprinted with permission. Publication Date: 6-10 Feb. 2005. The authors thank J. Tierno, T. Zwick, M. Beakes, S. Gowda, F. Friedman, M. Soyuer, M. Oprysko of IBM and J. Ewen of JDSU for technical feedback and support.
Subject Keywords:CMOS integrated circuits; adaptive equalisers; signal sampling; 0.13 micron; 1.2 V; 10 Gbit/s; 2D error diagram; 330 mW; CMOS; asymmetric eyes; eye-opening monitor
Record Number:CaltechAUTHORS:ANAisscc05
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:10906
Deposited By: Kristin Buxton
Deposited On:19 Jun 2008
Last Modified:26 Dec 2012 10:06

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