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A novel system architecture for real-time low-level vision

Benedetti, A. and Perona, P. (1999) A novel system architecture for real-time low-level vision. In: IEEE International Symposium on Circuits and Systems. ISCAS '99. Orlando, FL, 30 May-2 June 1999. Vol.3. IEEE , Piscataway, NJ, III-500-III-503. ISBN 0-7803-5471-0 http://resolver.caltech.edu/CaltechAUTHORS:BENiscas99

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Abstract

A novel system architecture that exploits the spatial locality in memory access that is found in most low-level vision algorithms is presented. A real-time feature selection system is used to exemplify the underlying ideas, and an implementation based on commercially available Field Programmable Gate Arrays (FPGA’s) and synchronous SRAM memory devices is proposed. The peak memory access rate of a system based on this architecture is estimated at 2.88 G-Bytes/s, which represents a four to five times improvement with respect to existing reconfigurable computers.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/ISCAS.1999.778892DOIUNSPECIFIED
http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=778892PublisherUNSPECIFIED
Additional Information:© Copyright 1999 IEEE. Reprinted with permission. Publication Date: 30 May-2 June 1999.
Subject Keywords:computer vision; feature extraction; field programmable gate arrays; real-time systems; reconfigurable architectures; video signal processing; memory access; real-time feature selection system; real-time low-level vision; spatial locality; synchronous SRAM memory devices; system architecture
Record Number:CaltechAUTHORS:BENiscas99
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:BENiscas99
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:11504
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:26 Aug 2008 18:28
Last Modified:26 Dec 2012 10:15

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