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Programmable neural logic

Bohossian, Vasken and Hasler, Paul and Bruck, Jehoshua (1997) Programmable neural logic. In: IEEE International Conference on Innovative Systems in Silicon, 2nd, Austin, TX, 8-10 October 1997. IEEE , Piscataway, NJ, pp. 13-21. ISBN 0-7803-4276-3 http://resolver.caltech.edu/CaltechAUTHORS:BOHiciss97

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Abstract

Circuits of threshold elements ( Boolean input, Boolean output neurons ) have been shown to be surprisingly powerful. Useful functions such as XOR, ADD and MULTIPLY can be implemented by such circuits more efficiently than by traditional AND/OR circuits. In view of that, we have designed and built a programmable threshold element. The weights are stored on polysilicon floating gates, providing long-term retention without refresh. The weight value is increased using tunneling and decreased via hot electron injection. A weight is stored on a single transistor allowing the development of dense arrays of threshold elements. A 16-input programmable neuron was fabricated in the standard 2 μm double - poly, analog process available from MOSIS. A long term goal of this research is to incorporate programmable threshold elements, as building blocks in Field Programmable Gate Arrays.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/ICISS.1997.630242DOIUNSPECIFIED
http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=630242PublisherUNSPECIFIED
Additional Information:© Copyright 1997 IEEE. Reprinted with permission. Publication Date: 8-10 Oct. 1997. This work was supported in part by the NSF Young Investigator Award CCR-9457811, by the Sloan Research Fellowship, by a grant from the IBM Almaden Research Center, San Jose, California, and by the center for Neuromorphic Systems Engineering as a part of the National Science Foundation Engineering Research Center Program; and by the California Trade and Commerce Agency, Office of Strategic Technology. The authors would like to thank the reviewers for their comments. Special thanks to Vincent Koosh for helping with the testing and analysis of the chip.
Funders:
Funding AgencyGrant Number
National Science FoundationCCR-9457811
Alfred P. Sloan FoundationUNSPECIFIED
IBM Almaden Research CenterUNSPECIFIED
Center for Neuromorphic Systems Engineering, CaltechUNSPECIFIED
California Trade and Commerce Agency, Office of Strategic TechnologyUNSPECIFIED
Subject Keywords:Boolean functions; VLSI; analogue processing circuits; hot carriers; neural chips; programmable logic devices; threshold logic; Boolean input; Boolean output; analogue VLSI; double-poly analog process; field programmable gate arrays; hot electron injection; polysilicon floating gates; programmable neural logic; programmable neuron; programmable threshold element; tunneling; weight value
Record Number:CaltechAUTHORS:BOHiciss97
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:BOHiciss97
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:11517
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:28 Aug 2008 01:11
Last Modified:26 Dec 2012 10:15

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