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Programmable neural logic

Bohossian, Vasken and Hasler, Paul and Bruck, Jehoshua (1998) Programmable neural logic. IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging,, 21 (4). pp. 346-351. ISSN 1070-9894. http://resolver.caltech.edu/CaltechAUTHORS:BOHieeetcpmtb98

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Abstract

Circuits of threshold elements (Boolean input, Boolean output neurons) have been shown to be surprisingly powerful. Useful functions such as XOR, ADD and MULTIPLY can be implemented by such circuits more efficiently than by traditional AND/OR circuits. In view of that, we have designed and built a programmable threshold element. The weights are stored on polysilicon floating gates, providing long-term retention without refresh. The weight value is increased using tunneling and decreased via hot electron injection. A weight is stored on a single transistor allowing the development of dense arrays of threshold elements. A 16-input programmable neuron was fabricated in the standard 2 μm double-poly, analog process available from MOSIS. We also designed and fabricated the multiple threshold element introduced in [5]. It presents the advantage of reducing the area of the layout from O(n^2) to O(n); (n being the number of variables) for a broad class of Boolean functions, in particular symmetric Boolean functions such as PARITY. A long term goal of this research is to incorporate programmable single/multiple threshold elements, as building blocks in field programmable gate arrays.


Item Type:Article
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http://dx.doi.org/10.1109/96.730415DOIUNSPECIFIED
http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=730415PublisherUNSPECIFIED
Additional Information:© Copyright 1998 IEEE. Reprinted with permission. Manuscript received March 22, 1998; revised August 7, 1998. This work was presented in part at the Second IEEE International Conference on Innovative Systems in Silicon, Austin, TX, October 1997. This work was supported in part by the NSF Young Investigator Award CCR-9457811, by the Sloan Research Fellowship, by a grant from the IBM Almaden Research Center, San Jose, CA, by the Center for Neuromorphic Systems Engineering as a part of the National Science Foundation Engineering Research Center Program; and by the California Trade and Commerce Agency, Office of Strategic Technology. The authors would like to thank the reviewers for their comments and V. Koosh for helping with the testing and analysis of the chip.
Funders:
Funding AgencyGrant Number
National Science FoundationCCR-9457811
Alfred P. Sloan FoundationUNSPECIFIED
IBM Almaden Research CenterUNSPECIFIED
Center for Neuromorphic Systems Engineering, CaltechUNSPECIFIED
California Trade and Commerce Agency, Office of Strategic TechnologyUNSPECIFIED
Subject Keywords:Boolean functions; circuit complexity; digital logic; floating gate; hot electron injection; threshold logic; tunneling; field programmable gate arrays; hot carriers; neural nets; Boolean output neurons; dense arrays; hot electron injection; long-term retention; multiple threshold element; polysilicon floating gates; programmable neural logic; symmetric Boolean functions; threshold elements; weight value
Record Number:CaltechAUTHORS:BOHieeetcpmtb98
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:BOHieeetcpmtb98
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:11518
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:28 Aug 2008 00:58
Last Modified:26 Dec 2012 10:15

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