Analui, Behnam and Rylyakov, Alexander and Rylov, Sergey and Meghelli, Mounir and Hajimiri, Ali (2005) A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS. IEEE Journal of Solid-State Circuits, 40 (12). pp. 2689-2699. ISSN 0018-9200. http://resolver.caltech.edu/CaltechAUTHORS:ANAieeejssc05
See Usage Policy.
Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechAUTHORS:ANAieeejssc05
An eye-opening monitor (EOM) architecture that can capture a two-dimensional (2-D) map of the eye diagram of a high-speed data signal has been developed. Two single-quadrant phase rotators and one digital-to-analog converter (DAC) are used to generate rectangular masks with variable sizes and aspect ratios. Each mask is overlapped with the received eye diagram and the number of signal transitions inside the mask is recorded as error. The combination of rectangular masks with the same error creates error contours that overall provide a 2-D map of the eye. The authors have implemented a prototype circuit in 0.13-μm standard CMOS technology that operates up to 12.5 Gb/s at 1.2-V supply. The EOM maps the input eye to a 2-D error diagram with up to 68-dB mask error dynamic range. The left and right halves of the eyes are monitored separately to capture horizontally asymmetric eyes. The chip consumes 330 mW and operates reliably with supply voltages as low as 1 V at 10 Gb/s. The authors also present a detailed analysis that verifies if the measurements are in good agreement with the expected results.
|Additional Information:||© Copyright 2005 IEEE. "Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.” Manuscript received April 11, 2005; revised July 25, 2005; Posted online: 2005-12-05. This work was supported by Caltech’s Lee Center for Advanced Networking and the National Science Foundation. The authors thank IBM Microelectronics for chip fabrication. They also acknowledge J. Tierno, T. Zwick, M. Beakes, S. Gowda, D. Friedman, M. Soyuer, and M. Oprysko of IBM T. J. Watson Research Center and J. Ewen of JDS-Uniphase for technical feedback and support. They thank J. Buckwalter from Caltech’s CHIC group for useful comments on the manuscript.|
|Subject Keywords:||Bit error rate, CMOS, eye diagram, eye monitor, eye-opening monitor, high speed, mask error rate, signal quality|
|Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Archive Administrator|
|Deposited On:||04 Jan 2006|
|Last Modified:||26 Dec 2012 08:43|
Repository Staff Only: item control page