Naeimi, Helia and DeHon, André (2004) A greedy algorithm for tolerating defective crosspoints in nanoPLA design. In: 2004 IEEE International Conference on Field-Programmable Technology. IEEE , Piscataway, NJ, pp. 49-56. ISBN 0-7803-8651-5 http://resolver.caltech.edu/CaltechAUTHORS:20110822-103525220
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Recent developments suggest both plausible fabrication techniques and viable architectures for building sublithographic programmable logic arrays using molecular-scale wires and switches. Designs at this scale will see much higher defect rates than in conventional lithography. However, these defects need not be an impediment to programmable logic design as this scale. We introduce a strategy for tolerating defective crosspoints and develop a linear-time, greedy algorithm for mapping PLA logic around crosspoint defects. We note that P-term fanin must be bounded to guarantee low overhead mapping and develop analytical guidelines for bounding fanin. We further quantify analytical and empirical mapping overhead rates. Including fanin bounding, our greedy mapping algorithm maps a large set of benchmark designs with 13% average overhead for random junction defect rates as high as 20%.
|Item Type:||Book Section|
|Additional Information:||© 2004 IEEE. Issue Date: 6-8 Dec. 2004. Date of Current Version: 14 February 2005. This research was funded in part by the DARPA Moletronics program under grant ONR N00014-01-0651 and N00014-04-1-0591.|
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|Official Citation:||Naeimi, H.; DeHon, A.; , "A greedy algorithm for tolerating defective crosspoints in nanoPLA design," Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on , vol., no., pp. 49- 56, 6-8 Dec. 2004 doi: 10.1109/FPT.2004.1393250 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1393250&isnumber=30303|
|Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Tony Diaz|
|Deposited On:||22 Aug 2011 17:49|
|Last Modified:||23 Aug 2016 10:04|
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