Sterling, Thomas and Brodowicz, Maciej (2005) Continuum Computer Architecture for Nano-scale and Ultra-high Clock Rate Technologies. In: Innovative Architecture for Future Generation High-Performance Processors and Systems. IEEE Computer Science , Los Alamitos, CA, pp. 101-109. ISBN 0-7695-2483-4 http://resolver.caltech.edu/CaltechAUTHORS:20110826-114759304
Full text not available from this repository.
Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechAUTHORS:20110826-114759304
Continuum computer architecture (CCA) is a non-von Neumann architecture that offers an alternative to conventional structures as digital technology evolves towards nano-scale and the ultimate flat-lining of Moore's law. Coincidentally, it also defines a model of architecture particularly well suited to logic classes that exhibit ultra-high clock rates (> 100 GHz) such as rapid single flux quantum (RSFQ) gates. CCA eliminates the concept of the "CPU" that has dominated computer architecture since its inception more than half a century ago and establishes a new local element that merges the properties of state storage, state transfer, and state operation. A CCA system architecture is a simple multidimensional organization of these elemental blocks and physically may be considered as a new family of cellular computer. But CCA differs dramatically from conventional cellular automata. While both deliver emergent global behavior from the aggregation of local rules and ensuing operation. The CCA emergent behavior is a global general-purpose model of parallel computation, as opposed to simply mimicking some limited phenomenon like heat and mass transfer as do conventional cellular automata. This paper presents the motivation and foundation concepts of CCA and exposes key issues for further work.
|Item Type:||Book Section|
|Additional Information:||© 2005 IEEE. Date of Current Version: 06 February 2006.|
|Official Citation:||Sterling, T.; Brodowicz, M.; , "Continuum computer architecture for nano-scale and ultra-high clock rate technologies," Innovative Architecture for Future Generation High-Performance Processors and Systems, 2005 , vol., no., pp. 9 pp., 17 Jan. 2005 doi: 10.1109/IWIA.2005.27|
|Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Ruth Sustaita|
|Deposited On:||26 Aug 2011 20:50|
|Last Modified:||26 Aug 2011 20:50|
Repository Staff Only: item control page