Buckwalter, James and Hajimiri, Ali (2004) An Active Analog Delay and the Delay Reference Loop. In: 2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. IEEE Radio Frequency Integrated Circuits Symposium. IEEE , Piscataway, N.J. , pp. 17-20. ISBN 0-7803-8333-8 http://resolver.caltech.edu/CaltechAUTHORS:20110916-101624435
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Wireline signal processing circuits such as transversal equalizers rely on true time delay. An active analog delay stage is proposed that requires a sixteenth of the area of a comparable LC delay line. A delay reference loop is also presented to tune the delay stage against process, voltage, and temperature variations. A reference signal is introduced to tune the delay. The impact of non-idealities must be considered, to understand the relationship between the reference frequency and the locked time delay. A SiGe BiCMOS implementation of the active analog delay stage and delay reference loop is presented that operates to 10 Gb/s.
|Item Type:||Book Section|
|Additional Information:||© 2004 IEEE. Issue Date: 6-8 June 2004. Date of Current Version: 09 August 2004. We would like to thank Behnam Analui and Hossein Hashemi for their guidance and the members of CHIC at Caltech for suggestions about the design, and IBM corp. for chip fabrication.|
|Subject Keywords:||delay reference loop; delay locked loop; true time delay; analog delay; equalization; tapped-delay lines|
|Other Numbering System:|
|Official Citation:||Buckwalter, J.; Hajimiri, A.; , "An active analog delay and the delay reference loop," Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE , vol., no., pp. 17- 20, 6-8 June 2004 doi: 10.1109/RFIC.2004.1320512|
|Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Ruth Sustaita|
|Deposited On:||19 Sep 2011 16:51|
|Last Modified:||19 Sep 2011 16:51|
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