Riedel, Marc D. and Bruck, Jehoshua (2004) Timing Analysis of Cyclic Combinatorial Circuits. California Institute of Technology , Pasadena. (Unpublished) http://resolver.caltech.edu/CaltechPARADISE:2004.ETR060
See Usage Policy.
Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechPARADISE:2004.ETR060
The accepted wisdom is that combinational circuits must have acyclic (i.e., loop-free or feed-forward) topologies. And yet simple examples suggest that this need not be so. In previous work, we advocated the design of cyclic combinational circuits (i.e., circuits with loops or feedback paths). We proposed a methodology for analyzing and synthesizing such circuits, with an emphasis on the optimization of area. In this paper, we extend our methodology into the temporal realm. We characterize the true delay of cyclic circuits through symbolic event propagation in the floating mode of operation, according to the up-bounded inertial delay model. We present analysis results for circuits optimized with our program CYCLIFY. Some benchmark circuits were optimized significantly, with simultaneous improvements of up to 10% in the area and 25% in the delay.
|Item Type:||Report or Paper (Technical Report)|
|Group:||Parallel and Distributed Systems Group|
|Usage Policy:||You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format|
|Deposited By:||Imported from CaltechPARADISE|
|Deposited On:||20 Aug 2004|
|Last Modified:||25 Feb 2014 22:00|
Repository Staff Only: item control page