Timing Analysis of Cyclic
Marc D. Riedel and Jehoshua Bruck
Proceedings of the International Workshop on Logic and Synthesis, Temecula Creek, CA, 2004
The accepted wisdom is that combinational circuits must have acyclic
(i.e., loop-free or feed-forward) topologies. And yet simple examples
suggest that this need not be so. In previous work, we advocated the
design of cyclic combinational circuits (i.e., circuits with loops
or feedback paths). We proposed a methodology for analyzing and
synthesizing such circuits, with an emphasis on the optimization of area.
In this paper, we extend our methodology into the temporal realm. We characterize the true delay of cyclic circuits through symbolic event propagation in the floating mode of operation, according to the up-bounded inertial delay model. We present analysis results for circuits optimized with our program CYCLIFY. Some benchmark circuits were optimized significantly, with simultaneous improvements of up to 10% in the area and 25% in the delay.