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Performance Analysis and Optimization of Asynchronous Circuits

Burns, Steven M. and Martin, Alain J. (1990) Performance Analysis and Optimization of Asynchronous Circuits. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1990.cs-tr-90-18

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Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:1990.cs-tr-90-18

Abstract

We present a method for analyzing the time performance of asynchronous circuits, in paxticulax, those derived by program transformation from concurrent programs using the synthesis approach developed by the second author. The analysis method produces a performance metric (related to the time needed to perform an operation) in terms of the primitive gate delays of the circuit. Such a metric provides a quantitative means by which to compare competing designs. Because the gate delays are functions of transistor sizes, the performance metric can be optimized with respect to these sizes. For a large class of asynchronous circuits-including those produced by using our synthesis method-these techniques produce the global optimum of the performance metric. A CAD tool has been implemented to perform this optimization.


Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Record Number:CaltechCSTR:1990.cs-tr-90-18
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1990.cs-tr-90-18
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26733
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:25 Apr 2001
Last Modified:26 Dec 2012 14:03

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