CaltechAUTHORS
  A Caltech Library Service

Performance Analysis and Optimization of Asynchronous Circuits

Burns, Steven M. (1991) Performance Analysis and Optimization of Asynchronous Circuits. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1991.cs-tr-91-01

[img]
Preview
Postscript
See Usage Policy.

8Mb
[img]
Preview
PDF
See Usage Policy.

6Mb

Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:1991.cs-tr-91-01

Abstract

Analytical techniques are developed to determine the performance of asynchronous digital circuits. These techniques can be used to guide the designer during the synthesis of such a circuit, leading to a high-performance, efficient implementation. Optimization techniques are also developed that further improve this implementation by determining the optimal sizes of the low-level devices (CMOS transistors) that compose the circuit.


Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Record Number:CaltechCSTR:1991.cs-tr-91-01
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1991.cs-tr-91-01
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26735
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:25 Apr 2001
Last Modified:26 Dec 2012 14:03

Repository Staff Only: item control page