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Tomorrow's Digital Hardware will be Asynchronous and Verified

Martin, Alain J. (1993) Tomorrow's Digital Hardware will be Asynchronous and Verified. Computer Science Technical Reports, California Institute of Technology , Pasadena, CA. (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1993.cs-tr-93-26

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Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:1993.cs-tr-93-26

Abstract

Encouraged by the results of almost a decade of research and experimentation, we claim that tomorrow's design methods for digital VLSI will be based on a concurrent programming approach to high-level synthesis, asynchronous techniques, and correctness-preserving program transformations.


Item Type:Report or Paper (Technical Report)
Additional Information:© 1993 California Institute of Technology. The research described in this paper would not have been possible without the contributions of my present and recent students. Dražen Borković, Steve Burns (now at the University of Washington), Marcel van der Goot, Pieter Hazewindus, Tony Lee, Christian Nielsen, and José Tierno. The insights, help, and encouragement of my Caltech colleague Charles L. Seitz are deeply appreciated. The research was sponsored by the Defense Advanced Research Projects Agency DARPA Order number and monitored by the Office of Naval Research under contract number N00014-87-K-0745.
Group:Computer Science Technical Reports
Funders:
Funding AgencyGrant Number
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
Office of Naval Research (ONR)N00014-87-K-0745
DOI:10.7907/Z9125QPR
Record Number:CaltechCSTR:1993.cs-tr-93-26
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1993.cs-tr-93-26
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26766
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:25 Apr 2001
Last Modified:19 Jun 2017 17:29

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