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Pipelined Asynchronous Circuits

Lines, Andrew Matthew (1998) Pipelined Asynchronous Circuits. California Institute of Technology , Pasadena, CA. (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1998.cs-tr-95-21

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Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:1998.cs-tr-95-21

Abstract

This thesis presents a design style for implementing communicating sequential processes (CSP) as quasi delay insensitive asynchronous circuits, based on the compilation method of [1]. Although hand compilation can always yield optimal circuits to a good designer, a restricted approach is suggested which can easily implement circuits with some slack between inputs and outputs. These circuits are fast and versatile building blocks for highly pipelined designs. The first chapter presents the implementation approach for individual cells. The second chapter investigates the time behavior of complex pipelined circuits, with the goal of adding slack where necessary and adjusting transistor sizes to optimize the overall throughput.


Item Type:Report or Paper (Technical Report)
Additional Information:© 1998 California Institute of Technology. June 1995, revised June 1998.
Group:Computer Science Technical Reports
DOI:10.7907/Z92V2D4Z
Record Number:CaltechCSTR:1998.cs-tr-95-21
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1998.cs-tr-95-21
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26834
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:30 Apr 2001
Last Modified:14 Mar 2017 15:09

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