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Low-Energy Asynchronous Memory Design

Tierno, Jose A. and Martin, Alain J. (1994) Low-Energy Asynchronous Memory Design. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1994.cs-tr-94-21

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Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:1994.cs-tr-94-21

Abstract

We introduce the concept of energy per operation as a measure of performance of an asynchronous circuit. We show how to model energy consumption based on the high-level language specification. This model is independent of voltage and timing considerations. We apply this model to memory design. We show first how to dimension a memory array, and how to break up this memory array into smaller arrays to minimize the energy per access. We then show how to use cache memory and pre-fetch mechanisms to further reduce energy per access.


Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Record Number:CaltechCSTR:1994.cs-tr-94-21
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1994.cs-tr-94-21
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26875
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:14 May 2001
Last Modified:26 Dec 2012 14:08

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