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On Detection and Generation of Dead-lock free Reshuffling in the VLSI Synthesis Method

Xu, Jiazhao Jessie (1996) On Detection and Generation of Dead-lock free Reshuffling in the VLSI Synthesis Method. California Institute of Technology , Pasadena, CA. (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1996.cs-tr-96-10

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Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:1996.cs-tr-96-10

Abstract

With the quick growth in the scale of VLSI circuits and the accordingly increasing complexity in the design of those large systems, the correctness of the design has demanded designers' attention. There are (recent) examples of microprocessors which have "bugs" in the designs and this raises questions about their reliability in performance. Personally, I am strongly against the popular use of word "bug" in the computer science world when people refer to their mistakes in the design. Mistake as defined by Webster is a wrong action or statement proceeding from faulty judgment, inadequate knowledge, or inattention; so it's not like a bug which crawls into our system on its own and ruins our life, but is a reflection of wrong decisions or of the inadequacy in our design methodology.


Item Type:Report or Paper (Technical Report)
Additional Information:© 1996 California Institute of Technology. May 26, 1995; revised on July 31, 1995.
Group:Computer Science Technical Reports
DOI:10.7907/Z9Q23X89
Record Number:CaltechCSTR:1996.cs-tr-96-10
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1996.cs-tr-96-10
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26891
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:14 May 2001
Last Modified:11 Apr 2017 16:53

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