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A Theory of Constant Et^2 CMOS Circuits

Papadantonakis, Karl (2001) A Theory of Constant Et^2 CMOS Circuits. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:2001.004

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Abstract

CMOS pulldown networks are characterized by their switching energy (E) and propagation delay (t), and voltage scaling has been shown to allow E or t to be adjusted, while Et^2 remains constant. Previously, this argument about single pulldown stages was applied to arbitrary digital circuits by assuming that the total delay of any such circuit was a sum of single pulldown and pullup stage delays, neglecting the time variation of the input to each stage. In this paper, the statement that Et^2 is independent of voltage scaling is generalized to arbitrary networks of CMOS transitors using only a weaker assumption: that every node has a capacitance.


Item Type:Report or Paper (Technical Report)
Additional Information:Caltech Asynchronous VLSI Group
Group:Computer Science Technical Reports
Subject Keywords:energy efficiency Et^2 CMOS circuits VLSI voltage scaling delay ODE
Record Number:CaltechCSTR:2001.004
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:2001.004
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26903
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:27 Sep 2001
Last Modified:26 Dec 2012 14:09

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