CaltechAUTHORS
  A Caltech Library Service

The Torus Routing Chip

Dally, William J. and Seitz, Charles L. (1986) The Torus Routing Chip. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1986.5208-tr-86

[img]
Preview
Other (Adobe PDF (1.6MB))
See Usage Policy.

1562Kb

Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:1986.5208-tr-86

Abstract

The torus routing chip (TRC) is a self-timed chip that performs deadlock-free cut-through routing in k-ary n-cube multiprocessor interconnection networks using a new method of deadlock avoidance called virtual channels. A prototype TRC with byte wide self-timed communication channels achieved on first silicon a throughput of 64Mbits/s in each dimension, about an order of magnitude better performance than the communication networks used by machines such as the Caltech Cosmic Cube or Intel iPSC. The latency of the cut-through routing of only 150ns per routing step largely eliminates message locality considerations in the concurrent programs for such machines. The design and testing of the TRC as a self-timed chip was no more difficult than it would have been for a synchronous chip.


Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Record Number:CaltechCSTR:1986.5208-tr-86
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1986.5208-tr-86
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26909
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:03 Dec 2001
Last Modified:26 Dec 2012 14:09

Repository Staff Only: item control page