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The design of high performance asynchronous circuits for the Caltech MiniMIPS processor

Pénzes, Paul I. (1998) The design of high performance asynchronous circuits for the Caltech MiniMIPS processor. California Institute of Technology , Pasadena, CA. (Unpublished) http://resolver.caltech.edu/CaltechCSTR:2002.001

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Abstract

The purpose of this report is to describe the design and implementation of an asynchronous Fetch unit used in the high-performance Caltech MiniMIPS microprocesors. The Caltech MiniMIPS microprocesors was designed based on the Martin synthesis techniques. The main goals of this project were to investigate new architectural issues in asyncronous processor design and to develop new techniques and tools that can meet high throughput requirements.


Item Type:Report or Paper (Technical Report)
Additional Information:© 1998 California Institute of Technology. Submitted May, 1998. I wish to thank the members of Asynchronous VLSI Group at Caltech for many stimulating discussions: Andrew Lines, Rajit Manohar, Mika Nyström, Robert Southworth and Catherine Wong. Special thanks to Rajit Mahonarfor designing and laying out the branch adder and for the very instructive discussion we had, to Uri Cummings for designing and laying out the incrementer and to Andrew Lines for the vehement debated we had ove the fetch. Last, but not least, thanks to Alain Marting for being my advisor and teaching me asynchronous VLSI.
Group:Computer Science Technical Reports
Subject Keywords:asynchronous VLSI
DOI:10.7907/Z90V89TB
Record Number:CaltechCSTR:2002.001
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:2002.001
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26924
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:11 Apr 2002
Last Modified:20 Mar 2017 18:24

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