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Global and local properties of asynchronous circuits optimized for energy efficiency

Penzes, Paul and Martin, Alain J. (2001) Global and local properties of asynchronous circuits optimized for energy efficiency. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:2002.002

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Abstract

In this paper we explore global and local properties of asynchronous circuits sized for the energy efficiency metric Et^2. We develop a theory that enables an abstract view on transistor sizing. These results allow us to accurately estimate circuit performance and compare circuit design choices at logic gate level without going through the costly sizing process. We estimate that the improvement in energy efficiency due to sizing is 2 to 3.5 times when compared to a design optimized for speed.


Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Subject Keywords:asynchronous, transistor sizing
Record Number:CaltechCSTR:2002.002
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:2002.002
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26925
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:11 Apr 2002
Last Modified:17 Jul 2014 21:27

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