Published April 11, 2002
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Transistor Sizing of Energy-Delay-Efficient Circuits
Abstract
This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay efficiency, i.e., for optimal Et^n where E is the energy consumption and t is the delay of the circuit, while n is a fixed positive optimization index that reflects the chosen trade-off between energy and delay. We propose a set of analytical formulas that closely approximate the optimal transistor sizes. We then study an efficient iteration procedure that can further improve the original analytical solution. Based on these results, we introduce a novel transistor sizing algorithm for energy-delay efficiency.
Additional Information
© 2002 California Institute of Technology. The authors thank Catherine Wong and Karl Papadantonakis for many stimulating discussions. The research reported in this paper was sponsored by the Defense Advanced Research Projects Agency and monitored by the Air Force under contract F29601-00-K-0184.Attached Files
Submitted - penzes.pdf
Submitted - penzes.ps
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Additional details
- Eprint ID
- 26926
- Resolver ID
- CaltechCSTR:2002.003
- Air Force Office of Scientific Research (AFOSR)
- F29601-00-K-0184
- Defense Advanced Research Projects Agency (DARPA)
- Created
-
2002-04-11Created from EPrint's datestamp field
- Updated
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2019-10-03Created from EPrint's last_modified field
- Caltech groups
- Computer Science Technical Reports