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Hot Clock nMOS

Seitz, Charles L. and Frey, Alexander H. and Mattisson, Sven and Rabin, Steve D. and Speck, Don A. and Snepscheut, Jan L. A. Van de (1985) Hot Clock nMOS. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1985.5177-tr-85

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Abstract

"Hot-Clock nMOS" is a style of design that has advantages in circuit energetics and performance. When the application of this style is carried to its limits, an nMOS chip is powered entirely from its clock signals. There are savings in area, delay, and power, even when the bootstrap circuits of this style are used together with conventional circuitry. We have used this technique in numerous small projects and test structures, and in 3 substantial projects fabricated through MOSIS.


Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Record Number:CaltechCSTR:1985.5177-tr-85
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1985.5177-tr-85
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26956
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:25 Jul 2002
Last Modified:26 Dec 2012 14:10

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