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A Graph Model and the Embedding of MOS Circuits

Ng, Tak-Kwong (1984) A Graph Model and the Embedding of MOS Circuits. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1983.5104-tr-83

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Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:1983.5104-tr-83

Abstract

The direct automated transformation of a circuit into the "best" physical layout is hard. An alternative is the transformation of a circuit into a suitable intermediate form, the layout topology. Each layout topology defines an equivalence class of physical layouts. A few layout topologies can be chosen according to their likeliness for leading to the "best" design. Each of these layout topologies can then be transformed into a physical layout that will be optimized. The final design can be chosen from the set of optimized physical layouts. Each optimized physical layout corresponds to a unique layout topology. A circuit is modeled as a graph, The circuit's graph model is analyzed by the embedding algorithm. The embedding algorithm determines the set of layout topologies that will be transformed into the physical layouts for further processing. A layout topology is specified as a graph together with the set of cyclic orders of the vertices, and the layer assignment of the edges.


Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Record Number:CaltechCSTR:1983.5104-tr-83
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1983.5104-tr-83
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26962
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:25 Jul 2002
Last Modified:26 Dec 2012 14:10

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