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A Self-Timed Chip Set for Microprocessor Communication

Whiting, Douglas L. (1982) A Self-Timed Chip Set for Microprocessor Communication. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1982.5000-tr-82

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Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:1982.5000-tr-82

Abstract

This paper describes a family of chips used to link multiple processors together on a speed-independent communication bus. Sendership arbitration is included as an integral part of the signalling scheme, incurring very little overhead and providing a measure of fairness. The protocol allows for one-to-many communication in which the sender must wait for all receivers to respond to each datum transmitted. The width of the data bus is arbitrary, and only three control wires are necessary for normal transmission cycles. In order to alleviate congestion, the global bus may be divided into several local buses by a method which is entirely transparent to the processor software. Thus the bus topology may be reconfigured for each processing network using these chips as building blocks. Functional verification of speed-independent circuits is also discussed. The problem is seen to be very complex, but some conclusions are drawn about the type of tools which will be helpful in implementing self-timed systems.


Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Record Number:CaltechCSTR:1982.5000-tr-82
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1982.5000-tr-82
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26988
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:07 Aug 2002
Last Modified:26 Dec 2012 14:11

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