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Residue Arithmetic and VLSI

Chiang, Chao-Lin and Johnsson, Lennart (1983) Residue Arithmetic and VLSI. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1983.5092-tr-83

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Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:1983.5092-tr-83

Abstract

In the residue number system arithmetic is carried out on each digit individually. There is no carry chain. This locality is of particular interest in VLSI. An evaluation of different implementations of residue arithmetic is carried out, and the effects of reduced feature sizes estimated. At the current state of technology the traditional table lookup method is preferable for a range that requires a maximum modulus that is represented by up to 4 bits, while an array of adders offers the best performance fur 7 or more bits. A combination of adders and tables covers 5 and 6 bits the best. At 0.5 mu m feature size table lookup is competitive only up to 3 bits, These conclusions are based on sample designs in nMOS.


Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Record Number:CaltechCSTR:1983.5092-tr-83
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1983.5092-tr-83
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:27001
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:07 Aug 2002
Last Modified:26 Dec 2012 14:12

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