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Speed and Energy Performance of an Asynchronous MIPS R3000 Microprocessor

Martin, Alain J. and Nyströem, Mika and Penzes, Paul and Wong, Catherine (2001) Speed and Energy Performance of an Asynchronous MIPS R3000 Microprocessor. California Institute of Technology , Pasadena, CA. (Unpublished) http://resolver.caltech.edu/CaltechCSTR:2001.012

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Abstract

This paper presents the speed and energy figures for an asynchronous implementation of a MIPS R3000 microprocessor. The design is almost entirely QDI and introduces a new fine-grained pipeline. The performance figures show that this design is four times as efficient as equivalent clocked designs and that its cycle time in FO4 units compares to that of high-performance dynamic pipelines.


Item Type:Report or Paper (Technical Report)
Additional Information:© 2001 California Institute of Technology. The research described in this paper was sponsored by the Defense Advanced Research Projects Agency and monitored by the Air Force under contract F29601-00-K-0184.
Group:Computer Science Technical Reports
Funders:
Funding AgencyGrant Number
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
Air Force Office of Scientific Research (AFOSR)F29601-00-K-0184
Subject Keywords:asynchronous VLSI, MIPS microprocessor, quasi delay-insensitive, energy-efficient, test results, asynchronous microprocessor
DOI:10.7907/Z99S1P11
Record Number:CaltechCSTR:2001.012
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:2001.012
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:27033
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:25 Sep 2002
Last Modified:07 Mar 2017 18:10

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