Martin, Alain J. and Nystroem, Mika and Penzes, Paul and Wong, Catherine (2001) Speed and Energy Performance of an Asynchronous MIPS R3000 Microprocessor. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:2001.012
See Usage Policy.
Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:2001.012
This paper presents the speed and energy figures for an asynchronous implementation of a MIPS R3000 microprocessor. The design is almost entirely QDI and introduces a new fine-grained pipeline. The performance figures show that this design is four times as efficient as equivalent clocked designs and that its cycle time in FO4 units compares to that of high-performance dynamic pipelines.
|Item Type:||Report or Paper (Technical Report)|
|Group:||Computer Science Technical Reports|
|Subject Keywords:||asynchronous VLSI, MIPS microprocessor, quasi delay-insensitive, energy-efficient, test results, asynchronous microprocessor|
|Usage Policy:||You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.|
|Deposited By:||Imported from CaltechCSTR|
|Deposited On:||25 Sep 2002|
|Last Modified:||26 Dec 2012 14:13|
Repository Staff Only: item control page