Seiler, Larry (1980) A Pascal Machine Architecture Implemented in Bristle Blocks, a Prototype Silicon Computer. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1980.2883-tr-80
See Usage Policy.
See Usage Policy.
Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechCSTR:1980.2883-tr-80
This thesis presents the multi-chip design of an architecture which directly implements the language Pascal. The design uses custom VLSl rather than standard chips in order to increase speed and reduce the number of chips needed. The integrated circuits comprising the architecture are designed using Bristle Blocks, a chip design tool developed at Caltech by Dave Johannsen (6). Bristle Blocks is called a silicon compiler because it will put together an entire integrated circuit from a high level description of its function. Bristle Blocks can be used to design datapath processor chips, where external microcode is used to control operations on data busses inside the chip. The Pascal machine architecture presented here is based on the EM-1 instruction set designed by Andrew Tannenbaum (11,13). The EM-1 instruction set is intended to allow efficient compilation of stack-based, high level languages. Tannenbaum supplies static frequency data which is used heavily in making design decisions in the Pascal machine architecture. VLSl design has several important differences from design using standard components. A large amount of function can be placed on a single chip, e.g., approximately 30,000 transistors on the Intel 8086, but only a small number of pins are available for off-chip communication (typically 64 or less). This requires designs to be highly modular. In the NMOS technology used at Caltech, driving signals off-chip takes up to ten times the time and energy of on-chip communication. This requires inter-chip communication to be limited as much as possible. Finally, the large amount of computing power available in VLSl encourages the use of concurrency to gain execution speed. This thesis is structured as follows. The thesis begins with a section defining the principles to be followed in designing the Pascal system architecture. Following that are sections describing Bristle Blocks and the EM-1 architecture. Next, the overall architecture of the Pascal machine is described, followed by sections detailing the system data busses, the common elements in the processors which make up the system, and the processors themselves. A conclusion section summarizes the work, provides a brief critique of Bristle Blocks, and includes recommendations for further work. Finally, the appendices document the Bristle Blocks datapath elements and the EM-1 instruction set.
|Item Type:||Report or Paper (Technical Report)|
|Group:||Computer Science Technical Reports|
|Usage Policy:||You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.|
|Deposited By:||Imported from CaltechCSTR|
|Deposited On:||03 Dec 2002|
|Last Modified:||26 Dec 2012 14:13|
Repository Staff Only: item control page