Papadantonakis, Karl (2003) An Asynchronous Register Bypass Transformation. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCSTR:2003.005
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A register specification typically states that in each cycle there is a possible read followed by a possible write; the sequence is strict. A register core with a separate read and write port is more efficient, because it can read and write to different locations simultaneously, and hence in one cycle. In the Caltech MiniMIPS processor, a control structure was added to such a register core, so that it implements the desired specification.
|Item Type:||Report or Paper (Technical Report)|
|Group:||Computer Science Technical Reports|
|Subject Keywords:||Register Bypass Asynchronous VLSI Program Transformation|
|Usage Policy:||You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.|
|Deposited By:||Imported from CaltechCSTR|
|Deposited On:||25 Jun 2003|
|Last Modified:||26 Dec 2012 14:14|
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