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An Architecture for Asynchronous FPGAs

Wong, Catherine G. and Martin, Alain J. and Thomas, Peter (2003) An Architecture for Asynchronous FPGAs. California Institute of Technology , Pasadena, CA. (Unpublished) http://resolver.caltech.edu/CaltechCSTR:2003.006

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Abstract

We present an architecture for a quasi delay-insensitive asynchronous field-programmable gate array. The logic cell is a complete asynchronous pipeline stage and the interconnects are entirely delay insensitive, eliminating all timing issues from the place-and-route procedure.


Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Subject Keywords:asynchronous vlsi, fpga
DOI:10.7907/Z9X9288B
Record Number:CaltechCSTR:2003.006
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:2003.006
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:27068
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:25 Aug 2003
Last Modified:07 Dec 2016 19:04

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