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An Architecture for Asynchronous FPGAs

Wong, Catherine G. and Martin, Alain J. and Thomas, Peter (2003) An Architecture for Asynchronous FPGAs. IEEE Computer Society Press . (In Press)

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We present an architecture for a quasi delay-insensitive asynchronous field-programmable gate array. The logic cell is a complete asynchronous pipeline stage and the interconnects are entirely delay insensitive, eliminating all timing issues from the place-and-route procedure.

Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Subject Keywords:FPGA, reconfigurable, asynchronous, delay-insensitive
Record Number:CaltechCSTR:2003.006a
Persistent URL:
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:27070
Deposited By: Imported from CaltechCSTR
Deposited On:05 Nov 2003
Last Modified:26 Dec 2012 14:14

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