Hashemi, Hossein and Hajimiri, Ali (2001) Concurrent Dual-Band CMOS Low Noise Amplifiers and Receiver Architectures. In: 2001 Symposium on VLSI Circuits. IEEE , Piscataway, NJ, pp. 247-250. ISBN 4-89114-014-3 http://resolver.caltech.edu/CaltechAUTHORS:20111117-120951431
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Abstract
A new concurrent dual-band receiver architecture is introduced that is capable of simultaneous operation at two different frequency bands. The concurrent operation results in higher bandwidth, lower total power dissipation and less sensitivity to channel variations. The architecture uses a novel concurrent dual-band low noise amplifier (LNA), combined with an elaborate frequency conversion scheme to reject the image bands. A general methodology for the design of concurrent LNAs is provided that makes it possible to achieve simultaneous narrowband gain and matching at multiple frequencies. The methodology is demonstrated by implementing an integrated dual-band concurrent LNA using 0.35 μm CMOS transistors. The LNA provides narrow-band gain and matching at 2.45 GHz and 5.25 GHz bands, simultaneously. It drains 4 mA of current and achieves voltage gains of 14 dB and 15.5 dB, input return losses of 25 dB and 15 dB, and noise figures of 2.3 dB and 4.5 dB at these two bands, respectively.
| Item Type: | Book Section | ||||
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| Additional Information: | © 2001 IEEE. Date of Current Version: 07 August 2002. The authors would like to thank members of Caltech Microelectronics and Microwave groups, particularly, I. Aoki, H. Wu, L. Chung, and S. Kee for assistance with measurements. We also thank Conexant Systems for chip fabrication, specially R. Magoon, F. Int’veld, and R. Hlavac. We appreciate helpful technical discussions with S. Weinreb of JPL, H. Samavati of Stanford University, and Y. Cheng of Conexant Systems. | ||||
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| Record Number: | CaltechAUTHORS:20111117-120951431 | ||||
| Persistent URL: | http://resolver.caltech.edu/CaltechAUTHORS:20111117-120951431 | ||||
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| Official Citation: | Hashemi, H.; Hajimiri, A.; , "Concurrent dual-band CMOS low noise amplifiers and receiver architectures," VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on , vol., no., pp.247-250, 2001 doi: 10.1109/VLSIC.2001.934254 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=934254&isnumber=20220 | ||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | ||||
| ID Code: | 27835 | ||||
| Collection: | CaltechAUTHORS | ||||
| Deposited By: | Ruth Sustaita | ||||
| Deposited On: | 17 Nov 2011 21:02 | ||||
| Last Modified: | 17 Nov 2011 21:02 |
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