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A Study of Multithreaded Benchmarks on the Hewlett-Packard X- and V-Class Architectures

Brunett, Sharon (1999) A Study of Multithreaded Benchmarks on the Hewlett-Packard X- and V-Class Architectures. California Institute of Technology . (Unpublished) http://resolver.caltech.edu/CaltechCACR:CACR-1999-173

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Abstract

The Hewlett-Packard X- and V-Class ccNUMA systems appear well suited to exploiting coarse and fine-grained parallelism, using multithreading techniques. This paper briefly summarizes the multilevel memory subsystem for the X- and V-Class platforms. Typical MPP distributed memory programming concerns for the codes under investigation, such as explicit memory localization and load balancing, are compared to relevant issues when porting and tuning for the X- and V-Class. This paper uses two small benchmarks as the basis for investigating differences running multithreaded codes in SPP-UX and HP-UX environments. One code is from the Command, Control, Communication and Intelligence (C3I) Parallel Benchmark suite, shown to have the potential for large-scale parallelization with straightforward multithreading techniques. The second benchmark exhibits the computationally dynamic behavior of a thermally-driven explosion model. Both codes are shown to stress the HP systems' ability to keep memory close to processors and appropriate threads of execution.


Item Type:Report or Paper (Technical Report)
Group:Center for Advanced Computing Research
Record Number:CaltechCACR:CACR-1999-173
Persistent URL:http://resolver.caltech.edu/CaltechCACR:CACR-1999-173
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:28166
Collection:CaltechCACR
Deposited By: Imported from CaltechCACR
Deposited On:18 Mar 2004
Last Modified:26 Dec 2012 14:31

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