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The "MIND" Scalable PIM Architecture

Sterling, Thomas and Brodowicz, Maciej (2005) The "MIND" Scalable PIM Architecture. In: Advanced Research Workshop on High Performance Computing Technology and Applications, 31 May-3 June, 2004, Cetraro, Italy. (Submitted) http://resolver.caltech.edu/CaltechCACR:2005.102

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Abstract

MIND (Memory, Intelligence, and Network Device) is an advanced parallel computer architecture for high performance computing and scalable embedded processing. It is a Processor-in-Memory (PIM) architecture integrating both DRAM bit cells and CMOS logic devices on the same silicon die. MIND is multicore with multiple memory/processor nodes on each chip and supports global shared memory across systems of MIND components. MIND is distinguished from other PIM architectures in that it incorporates mechanisms for efficient support of a global parallel execution model based on the semantics of message-driven multithreaded split-transaction processing. MIND is designed to operate either in conjunction with other conventional microprocessors or in standalone arrays of like devices. It also incorporates mechanisms for fault tolerance, real time execution, and active power management. This paper describes the major elements and operational methods of the MIND architecture.


Item Type:Conference or Workshop Item (Paper)
Group:Center for Advanced Computing Research
Record Number:CaltechCACR:2005.102
Persistent URL:http://resolver.caltech.edu/CaltechCACR:2005.102
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:28210
Collection:CaltechCACR
Deposited By: Imported from CaltechCACR
Deposited On:20 Apr 2005
Last Modified:26 Dec 2012 14:32

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