Blaum, Mario and Bruck, Jehoshua and Pifarré, Gustavo D. and Sanz, Jorge L. C. (1996) On Optimal Placements of Processors in Tori Networks. In: Eighth IEEE Symposium on Parallel and Distributed Processing. IEEE Computer Society , Los Alamitos, CA, pp. 552-555. ISBN 0-8186-7683-3 http://resolver.caltech.edu/CaltechAUTHORS:20120207-113452642
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Two and three dimensional k-tori are among the most used topologies in the designs of new parallel computers. Traditionally (with the exception of the Tera parallel computer), these networks have been used as fully-populated networks, in the sense that every routing node in the topology is subjected to message injection. However, fully populated tori and meshes exhibit a theoretical throughput which degrades as the network size increases. In contrast, multistage networks (that are partially populated) scale well with the network size. Introducing slackness in fully populated tori, i.e., reducing the number of processors, and studying optimal routing strategies for the resulting interconnections are the central subjects of the paper. The key concept is the placement of the processors in a network together with a routing algorithm between them, where a placement is the subset of the nodes in the interconnection network that are attached to processors. The main contribution is the construction of optimal placements for d-dimensional k-tori networks, of sizes k and k^2 and the corresponding routing algorithms for the cases d=2 and d=3, respectively.
|Item Type:||Book Section|
|Additional Information:||© 1996 IEEE. Date of Current Version: 06 August 2002. Supported in part by the NSF Young Investigator Award CCR-9457811, by the Sloan Research Fellowship and by a grant from the IBM Almaden Research Center, San Jose, California. Supported in part by the Universidad de Buenos Aim through the research project EX-155 and through the scholarships program Rene Hugo Thalman.|
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|Official Citation:||Blaum, M.; Bruck, J.; Pifarre, G.D.; Sanz, J.L.C.; , "On optimal placements of processors in tori networks," Parallel and Distributed Processing, 1996. Eighth IEEE Symposium on , vol., no., pp.552-555, 23-26 Oct 1996 doi: 10.1109/SPDP.1996.570382 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=570382&isnumber=12269|
|Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Ruth Sustaita|
|Deposited On:||07 Feb 2012 23:56|
|Last Modified:||07 Feb 2012 23:56|
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