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Switch-Level Modeling of MOS Digital Circuits

Bryant, Randal E. (1982) Switch-Level Modeling of MOS Digital Circuits. California Institute of Technology , Pasadena, CA. (Unpublished) http://resolver.caltech.edu/CaltechAUTHORS:20120419-112428166

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Abstract

The switch-level model describes the logical behavior of digital circuits implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X, and each transistor having a state open, closed, or unknown. The logic simulator MOSSIM II has been implemented with this model as its basis. MOSSIM II can simulate a wide variety of MOS circuits at speeds approaching those of event-driven logic gate simulators. The simulator can apply additional tests to detect potential timing errors, unrestored logic levels in CMOS, and unrefreshed dynamic charge. This paper provides an overview of the switch-level model and how it is applied in MOSSIM II.


Item Type:Report or Paper (Technical Report)
Additional Information:This paper will appear in the Proceedings of ISCAS 1982. This work was funded in part by Defense Advanced Research Contracts Agency ARPA Order Number 3771 and by the Caltech Silicon Structures Project.
Group:Computer Science Technical Reports
Funders:
Funding AgencyGrant Number
Defense Advanced Research Projects Agency (DARPA)ARPA order 3771
Caltech Silicon Structures ProjectUNSPECIFIED
Other Numbering System:
Other Numbering System NameOther Numbering System ID
Computer Science Technical Memorandum5012
Record Number:CaltechAUTHORS:20120419-112428166
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20120419-112428166
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:30201
Collection:CaltechCSTR
Deposited By: Kristin Buxton
Deposited On:01 May 2012 21:12
Last Modified:26 Dec 2012 15:05

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