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Minimum propagation delays in VLSI

Mead, Carver and Rem, Martin (1983) Minimum propagation delays in VLSI. California Institute of Technology , Pasadena, CA. (Unpublished) http://resolver.caltech.edu/CaltechAUTHORS:20120420-104637505

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Abstract

In this paper we demonstrate that it is possible to achieve propagation delays that are logarithmic in the lengths of the wires, provided the connection pattern is designed to meet rather strong constraints. These constraints are, in effect, satisfied only by connection patterns that exhibit a hierarchical structure. We also show that, even at the ultimate physical limits of the technology, the propagation for reasonably sized VLSI chips is dominated by these considerations, rather than by the speed of light.


Item Type:Report or Paper (Technical Report)
Additional Information:Copyright, California Institute of Technology, 1981. The research described in this paper was sponsored by the Office of Naval Research Contract No. N00014-76-C-0367 and by the Defense Advanced Research Agency, ARPA Order number 3771, and monitored by the Office of Naval Research under Contract number N00014-79-C-0597.
Group:Computer Science Technical Reports
Funders:
Funding AgencyGrant Number
Office of Naval ResearchN00014-76-C-0367
Defense Advanced Research Projects Agency (DARPA)ARPA order 3771
Other Numbering System:
Other Numbering System NameOther Numbering System ID
Computer Science Technical Memorandum4601
Record Number:CaltechAUTHORS:20120420-104637505
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20120420-104637505
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:30220
Collection:CaltechCSTR
Deposited By: Kristin Buxton
Deposited On:02 May 2012 17:51
Last Modified:26 Dec 2012 15:05

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