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A 10Gb/s data-dependent jitter equalizer

Buckwalter, James and Hajimiri, Ali (2004) A 10Gb/s data-dependent jitter equalizer. In: IEEE Custom Integrated Circuits Conference, 2004, Orlando, FL, 3-6 October 2004. IEEE , Piscataway, NJ, pp. 39-42. ISBN 0-7803-8495-4

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An equalization circuit is presented that reduces data-dependent jitter by aligning data transition deviations. This paper presents an analytic solution to data-dependent jitter and demonstrates its impact on the phase noise of the recovered clock. A data-dependent jitter equalizer is presented that compensates for impairment of the channel and lowers the phase noise of the recovered clock. The circuit is implemented in a SiGe BiCMOS process and operates at 10 Gb/s. It suppresses phase noise resulting from data-dependent jitter by 10 dB.

Item Type:Book Section
Additional Information:© Copyright 2004 IEEE. Reprinted with permission
Subject Keywords:BiCMOS integrated circuits, equalisers, phase noise, synchronisation, timing jitter
Record Number:CaltechAUTHORS:BUCcicc04
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:3158
Deposited By: Archive Administrator
Deposited On:17 May 2006
Last Modified:26 Dec 2012 08:52

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