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A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation

Nazari, Meisam Honarvar and Emami-Neyestanak, Azita (2012) A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation. IEEE Journal of Solid-State Circuits, 47 (10). pp. 2420-2432. ISSN 0018-9200. http://resolver.caltech.edu/CaltechAUTHORS:20121116-132920248

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Abstract

This paper presents a low-power receiver with two-tap decision feedback equalization (DFE) and novel far-end crosstalk (FEXT) cancellation capability, implemented in a 45-nm SOI CMOS process. The receiver employs a half-rate speculative DFE architecture to allow for the use of low-power front-end circuitry and CMOS clock buffers. In the proposed architecture, a switched-capacitor sample-hold at the front-end is employed to perform DFE tap summation. This technique is generalized to implement n taps of equalization. The receiver compensates the effect of crosstalk without making a decision on the received aggressor signal. Due to the low-power nature of the switched-capacitor front-end, the crosstalk cancellation is possible with only 33 μW/Gbps/lane power overhead. The receiver was tested over channels with different levels of loss and coupling. The signaling rate with BER < 10^(-12) was significantly increased with the use of DFE and crosstalk cancellation scheme for highly coupled and lossy PCB traces. The DFE receiver equalizes 15-Gb/s data over a channel with more than 14-dB loss while consuming about 7.5 mW from a 1.2-V supply. At lower data rates it equalizes channels with over 21-dB loss.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/JSSC.2012.2203870DOIUNSPECIFIED
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6248710PublisherUNSPECIFIED
Additional Information:© 2012 IEEE. Manuscript received December 19, 2011; revised May 31, 2012; accepted June 01, 2012. This paper was approved by Associate Editor Jan Craninckx. This work was supported in part by the National Science Foundation, intel, and the C2S2 Focus Center, through the Focus Center Research Program. The authors would like to thank IBM for chip fabrication. M. Nazari would also like to thank Z. Safarian for constant help and support.
Funders:
Funding AgencyGrant Number
NSFUNSPECIFIED
IntelUNSPECIFIED
C2S2 Focus Center Focus Center Research ProgramUNSPECIFIED
Subject Keywords:Decision feedback equalization (DFE); far-end crosstalk (FEXT); interconnects; receiver; speculative; summation; switched capacitor (SC)
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INSPEC Accession Number13030240
Record Number:CaltechAUTHORS:20121116-132920248
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20121116-132920248
Official Citation:Nazari, M.H.; Emami-Neyestanak, A.; , "A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation," Solid-State Circuits, IEEE Journal of , vol.47, no.10, pp.2420-2432, Oct. 2012 doi: 10.1109/JSSC.2012.2203870 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6248710&isnumber=6320632
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:35520
Collection:CaltechAUTHORS
Deposited By: Jason Perez
Deposited On:17 Nov 2012 00:10
Last Modified:17 Nov 2012 00:10

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