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A Modular Multi-Chip Neuromorphic Architecture for Real-Time Visual Motion Processing

Higgins, Charles M. and Koch, Christof (2000) A Modular Multi-Chip Neuromorphic Architecture for Real-Time Visual Motion Processing. Analog Integrated Circuits and Signal Processing, 24 (3). pp. 195-211. ISSN 0925-1030. http://resolver.caltech.edu/CaltechAUTHORS:20130816-103146617

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Abstract

The extent of pixel-parallel focal plane image processing is limited by pixel area and imager fill factor. In this paper, we describe a novel multi-chip neuromorphic VLSI visual motion processing system which combines analog circuitry with an asynchronous digital interchip communications protocol to allow more complex pixel-parallel motion processing than is possible in the focal plane. This multi-chip system retains the primary advantages of focal plane neuromorphic image processors: low-power consumption, continuous-time operation, and small size. The two basic VLSI building blocks are a photosensitive sender chip which incorporates a 2D imager array and transmits the position of moving spatial edges, and a receiver chip which computes a 2D optical flow vector field from the edge information. The elementary two-chip motion processing system consisting of a single sender and receiver is first characterized. Subsequently, two three-chip motion processing systems are described. The first three-chip system uses two sender chips to compute the presence of motion only at a particular stereoscopic depth from the imagers. The second three-chip system uses two receivers to simultaneously compute a linear and polar topographic mapping of the image plane, resulting in information about image translation, rotation, and expansion. These three-chip systems demonstrate the modularity and flexibility of the multi-chip neuromorphic approach.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1023/A:1008309524326DOIArticle
http://link.springer.com/article/10.1023/A%3A1008309524326PublisherArticle
Additional Information:c2000 Kluwer Academic Publishers. Received September 3, 1999; Revised January 27, 2000. The authors gratefully acknowledge Kwabena Boahen for his copious assistance in explaining his implementation of the AER protocol, and would also like to thank Tim Horiuchi for helpful suggestions, and Rainer Deutschmann for comments on the manuscript. This research was supported by the Center for Neuromorphic Systems Engineering as a part of the National Science Foundation's Engineering Research Center program as well as by the Office of Naval Research. The authors wish to thank the anonymous reviewers for their help in clarifying this paper.
Group:Koch Laboratory, KLAB
Funders:
Funding AgencyGrant Number
Center for Neuromorphic Systems Engineering, CaltechUNSPECIFIED
Engineering Research Center at CaltechUNSPECIFIED
U.S. Office of Naval Research UNSPECIFIED
Subject Keywords:analog VLSI, vision chips, optical flow, stereo, neuromorphic
Record Number:CaltechAUTHORS:20130816-103146617
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20130816-103146617
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:40394
Collection:CaltechAUTHORS
Deposited By: KLAB Import
Deposited On:11 Jan 2008 22:39
Last Modified:23 Sep 2013 19:42

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