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How tunneling currents reduce plasma-induced charging

Hwang, Gyeong S. and Giapis, Konstantinos P. (1997) How tunneling currents reduce plasma-induced charging. Applied Physics Letters, 71 (20). pp. 2928-2930. ISSN 0003-6951. http://resolver.caltech.edu/CaltechAUTHORS:HWAapl97a

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Abstract

As semiconductor manufacturing moves towards smaller logic devices and thinner gate oxides, there is serious concern that pattern-dependent charging during plasma etching will impede progress by distorting etch profiles and by causing oxide breakdown. Simulations of the final overetch predict that the use of ultrathin oxides (<= 5 nm), combined with a low substrate potential, will actually eliminate notching by enabling electron tunneling from the substrate to decrease surface charging potentials at the bottom of high aspect ratio trenches. Comparison with published experimental results validates the simulations.


Item Type:Article
Additional Information:©1997 American Institute of Physics. (Received 24 June 1997; accepted 18 September 1997) This work was supported by an NSF-Career Award and a Camille Dreyfus Teacher-Scholar Award to KPG.
Subject Keywords:sputter etching; surface charging; tunnelling; semiconductor technology
Record Number:CaltechAUTHORS:HWAapl97a
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:HWAapl97a
Alternative URL:http://dx.doi.org/10.1063/1.120218
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:4806
Collection:CaltechAUTHORS
Deposited By: Archive Administrator
Deposited On:07 Sep 2006
Last Modified:26 Dec 2012 09:01

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