Hwang, Gyeong S. and Giapis, Konstantinos P. (1997) Simulation of current transients through ultrathin gate oxides during plasma etching. Applied Physics Letters, 71 (14). pp. 1945-1947. ISSN 0003-6951. http://resolver.caltech.edu/CaltechAUTHORS:HWAapl97b
See Usage Policy.
Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechAUTHORS:HWAapl97b
Monte Carlo simulations of electron tunneling through a 3 nm gate oxide during etching of dense patterns of gate electrodes in uniform high-density plasmas reveal two current transients, which occur: (a) when the open area clears, and (b) when the polysilicon lines just become disconnected at the bottom of trenches. The first charging transient is fast (controlled by charging) and may be followed by a steady-state current which lasts until the lines get disconnected. The second charging transient lasts longer; the magnitude of the tunneling current generally decreases as the sloped polysilicon sidewalls become straighter. Most of the damage occurs at the edge gate when the open areas are covered by field oxide; however, the edge gate suffers no damage when the 3 nm oxide extends into the open areas.
|Additional Information:||©1997 American Institute of Physics. (Received 25 June 1997; accepted 2 August 1997) This work was supported by a Camille Dreyfus Teacher-Scholar Award to KPG.|
|Subject Keywords:||transients; sputter etching; silicon; Monte Carlo methods; tunnelling; semiconductor process modelling; semiconductor-insulator boundaries|
|Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Archive Administrator|
|Deposited On:||07 Sep 2006|
|Last Modified:||26 Dec 2012 09:01|
Repository Staff Only: item control page