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Quantifying Near-Threshold CMOS Circuit Robustness

Keller, Sean and Bhargav, Siddharth S. and Moore, Chris and Martin, Alain J. (2014) Quantifying Near-Threshold CMOS Circuit Robustness. California Institute of Technology , Pasadena, CA. (Unpublished) http://resolver.caltech.edu/CaltechAUTHORS:20141125-133400175

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Abstract

In order to build energy efficient digital CMOS circuits, the supply voltage must be reduced to near-threshold. Problematically, due to random parameter variation, supply scaling reduces circuit robustness to noise. Moreover, the effects of parameter variation worsen as device dimensions diminish, further reducing robustness, and making parameter variation one of the most significant hurdles to continued CMOS scaling. This paper presents a new metric to quantify circuit robustness with respect to variation and noise along with an efficient method of calculation. The method relies on the statistical analysis of standard cells and memories resulting an an extremely compact representation of robustness data. With this metric and method of calculation, circuit robustness can be included alongside energy, delay, and area during circuit design and optimization.


Item Type:Report or Paper (Technical Report)
Additional Information:© 2014 California Institute of Technology.
Group:Computer Science Technical Reports
Other Numbering System:
Other Numbering System NameOther Numbering System ID
CaltechCSTR2014.002
DOI:10.7907/Z9M043CG
Record Number:CaltechAUTHORS:20141125-133400175
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20141125-133400175
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:52152
Collection:CaltechCSTR
Deposited By: Kristin Buxton
Deposited On:25 Nov 2014 21:46
Last Modified:13 Dec 2016 00:47

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