DeHon, André and Naeimi, Helia (2005) Seven strategies for tolerating highly defective fabrication. IEEE Design and Test of Computers, 22 (4). pp. 306-315. ISSN 0740-7475 http://resolver.caltech.edu/CaltechAUTHORS:DEHieeedtc05
See Usage Policy.
Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechAUTHORS:DEHieeedtc05
In this article we present an architecture that supports fine-grained sparing and resource matching. The base logic structure is a set of interconnected PLAs. The PLAs and their interconnections consist of large arrays of interchangeable nanowires, which serve as programmable product and sum terms and as programmable interconnect links. Each nanowire can have several defective programmable junctions. We can test nanowires for functionality and use only the subset that provides appropriate conductivity and electrical characteristics. We then perform a matching between nanowire junction programmability and application logic needs to use almost all the nanowires even though most of them have defective junctions. We employ seven high-level strategies to achieve this level of defect tolerance.
|Additional Information:||© Copyright 2005 IEEE. Reprinted with permission. We thank the Defense Advanced Research Projects Agency for supporting this research under Office of Naval Research contract N00014-04-1-0591. This material is based on work supported by the Department of the Navy, Office of Naval Research. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the Office of Naval Research.|
|Subject Keywords:||fault tolerance; field programmable gate arrays; molecular electronics; nanotechnology; nanowires; redundancy|
|Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Archive Administrator|
|Deposited On:||06 Oct 2006|
|Last Modified:||26 Dec 2012 09:04|
Repository Staff Only: item control page