Mead, Carver A. (1994) Scaling of MOS technology to submicrometer feature sizes. Journal of VLSI Signal Processing, 8 (1). pp. 9-25. ISSN 0922-5773. http://resolver.caltech.edu/CaltechAUTHORS:20150109-125350741
Full text is not posted in this repository. Consult Related URLs below.
Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechAUTHORS:20150109-125350741
Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the attendant changes in device behavior, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.
|Additional Information:||© 1994 Kluwer Academic Publishers. Received June 8, 1993; Revised July 27, 1993.|
|Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Kristin Buxton|
|Deposited On:||09 Jan 2015 21:25|
|Last Modified:||09 Jan 2015 21:25|
Repository Staff Only: item control page