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The influence of interface states on incomplete charge transfer in overlapping gate charge-coupled devices

Mohsen, Amr M. and McGill, T. C. and Daimon, Yoshiaki and Mead, Carver A. (1973) The influence of interface states on incomplete charge transfer in overlapping gate charge-coupled devices. IEEE Journal of Solid-State Circuits, 8 (2). pp. 125-138. ISSN 0018-9200. http://resolver.caltech.edu/CaltechAUTHORS:20150113-162610060

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Abstract

A simple and accurate model is used to estimate the incomplete charge transfer due to interface states trapping in the overlapping gate charge-coupled devices. It is concluded that trapping in the interface states under the edges of the gates parallel to the active channel limits the performance of the devices at moderate and low frequencies. The influence of the device parameters, dimensions, and clocking waveforms on the signal degradation is discussed. It is shown that increasing the clock voltages, reduces the incomplete charge transfer due to interface state trapping.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/JSSC.1973.1050361DOIArticle
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1050361PublisherArticle
Additional Information:© 1973 IEEE. Manuscript received October 23, 1972. This work was supported in part by the Office of Naval Research (A. Shostak) and the Naval Research Laboratory (D. F. Barbe).
Funders:
Funding AgencyGrant Number
Office of Naval Research (ONR)UNSPECIFIED
Naval Research LaboratoryUNSPECIFIED
Record Number:CaltechAUTHORS:20150113-162610060
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20150113-162610060
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:53663
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:14 Jan 2015 06:32
Last Modified:14 Jan 2015 06:32

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